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<head><meta charset="utf-8"><title>LLVM IR semantics · t-lang · Zulip Chat Archive</title></head>
<h2>Stream: <a href="https://rust-lang.github.io/zulip_archive/stream/213817-t-lang/index.html">t-lang</a></h2>
<h3>Topic: <a href="https://rust-lang.github.io/zulip_archive/stream/213817-t-lang/topic/LLVM.20IR.20semantics.html">LLVM IR semantics</a></h3>

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<a name="200978945"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/213817-t-lang/topic/LLVM%20IR%20semantics/near/200978945" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> RalfJ <a href="https://rust-lang.github.io/zulip_archive/stream/213817-t-lang/topic/LLVM.20IR.20semantics.html#200978945">(Jun 16 2020 at 06:57)</a>:</h4>
<p><a href="https://blog.regehr.org/archives/1737">https://blog.regehr.org/archives/1737</a> is an excellent blog post on LLVM IR semantics. Many of the concerns there apply to Rust, in particular those in "Other issues". The FP issue is <a href="https://github.com/rust-lang/rust/issues/73328">https://github.com/rust-lang/rust/issues/73328</a>. "Load widening" and "inttoptr(ptrtoint(x)) =&gt; x" is something I mention occasionally.</p>
<p>The one I haven't seen is "Shufflevector semantics". What are the Rust-side rules here for OOB shufflevector masks -- is it just UB and so we are fine no matter what LLVM decides?<br>
Cc <span class="user-group-mention" data-user-group-id="1176">@WG-llvm</span> <span class="user-mention" data-user-id="143274">@Amanieu</span></p>



<a name="200986139"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/213817-t-lang/topic/LLVM%20IR%20semantics/near/200986139" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Hanna Kruppe <a href="https://rust-lang.github.io/zulip_archive/stream/213817-t-lang/topic/LLVM.20IR.20semantics.html#200986139">(Jun 16 2020 at 08:32)</a>:</h4>
<p>I don't think we have any generic shufflevector-like operation in stable (the intrinsic used to implement some core::arch functions is unstable), so we shouldn't be constrained here. If it's not already spelled out then I agree we should just make OOB indices UB. More generally, LLVM's <code>shufflevector</code> is very clever and general to represent a million different patterns in one instruction, but there's no reason to mirror this in Rust interfaces, we can just have dedicated intrinsics for different patterns that side-step these tricky aspects.</p>



<a name="201024158"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/213817-t-lang/topic/LLVM%20IR%20semantics/near/201024158" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Lokathor <a href="https://rust-lang.github.io/zulip_archive/stream/213817-t-lang/topic/LLVM.20IR.20semantics.html#201024158">(Jun 16 2020 at 14:34)</a>:</h4>
<p>I am not aware of the shuffle const being constrained other than by the standard "the intrinsic does what the Intel docs say", and they don't say UB for an OOB const, so right now it's not UB.</p>
<p>In the <code>safe_arch</code> crate I do use masking to only allow in-bounds values to be generated.</p>



<a name="201034629"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/213817-t-lang/topic/LLVM%20IR%20semantics/near/201034629" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Amanieu <a href="https://rust-lang.github.io/zulip_archive/stream/213817-t-lang/topic/LLVM.20IR.20semantics.html#201034629">(Jun 16 2020 at 15:45)</a>:</h4>
<p>Since the mask must be a compile-time constant I think it is implied that the compiler is expected to error if an invalid value is passed in.</p>



<a name="201471429"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/213817-t-lang/topic/LLVM%20IR%20semantics/near/201471429" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> RalfJ <a href="https://rust-lang.github.io/zulip_archive/stream/213817-t-lang/topic/LLVM.20IR.20semantics.html#201471429">(Jun 20 2020 at 10:12)</a>:</h4>
<p>but then if this is so trivial to detect at compiletime, why does LLVM not do that?</p>



<a name="201472442"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/213817-t-lang/topic/LLVM%20IR%20semantics/near/201472442" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Hanna Kruppe <a href="https://rust-lang.github.io/zulip_archive/stream/213817-t-lang/topic/LLVM.20IR.20semantics.html#201472442">(Jun 20 2020 at 10:43)</a>:</h4>
<p>I can only guess, but in other situations similar to this, some relevant concerns are: backwards compatibility (specifically, ability to upgrade old IR), hard errors being undesirable if it occurs in dead code (e.g., from C++ template instantiations), and hard-UB (instead of poison/undef result) creating a footgun for code hoisting transforms.</p>



<a name="201472505"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/213817-t-lang/topic/LLVM%20IR%20semantics/near/201472505" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Hanna Kruppe <a href="https://rust-lang.github.io/zulip_archive/stream/213817-t-lang/topic/LLVM.20IR.20semantics.html#201472505">(Jun 20 2020 at 10:44)</a>:</h4>
<p>The first point might be particular important since shufflevector semantics in general are... very old and organically-grown.</p>



<a name="201472743"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/213817-t-lang/topic/LLVM%20IR%20semantics/near/201472743" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> RalfJ <a href="https://rust-lang.github.io/zulip_archive/stream/213817-t-lang/topic/LLVM.20IR.20semantics.html#201472743">(Jun 20 2020 at 10:52)</a>:</h4>
<p>okay, I see</p>



<a name="201472750"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/213817-t-lang/topic/LLVM%20IR%20semantics/near/201472750" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> RalfJ <a href="https://rust-lang.github.io/zulip_archive/stream/213817-t-lang/topic/LLVM.20IR.20semantics.html#201472750">(Jun 20 2020 at 10:53)</a>:</h4>
<p>so if we agree that rustc should just reject OOB indices statically for now... is that currently implemented and tested?</p>



<a name="201473154"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/213817-t-lang/topic/LLVM%20IR%20semantics/near/201473154" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Hanna Kruppe <a href="https://rust-lang.github.io/zulip_archive/stream/213817-t-lang/topic/LLVM.20IR.20semantics.html#201473154">(Jun 20 2020 at 11:04)</a>:</h4>
<p>Nope: <a href="https://play.rust-lang.org/?version=nightly&amp;mode=debug&amp;edition=2018&amp;gist=3e5c8da20683871a552d0b4067a3f8cc">https://play.rust-lang.org/?version=nightly&amp;mode=debug&amp;edition=2018&amp;gist=3e5c8da20683871a552d0b4067a3f8cc</a></p>



<a name="201473223"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/213817-t-lang/topic/LLVM%20IR%20semantics/near/201473223" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Hanna Kruppe <a href="https://rust-lang.github.io/zulip_archive/stream/213817-t-lang/topic/LLVM.20IR.20semantics.html#201473223">(Jun 20 2020 at 11:06)</a>:</h4>
<p>But I don't know if we can <em>just</em> prohibit it. There might be some std::arch intrinsics using "shufflevector that results in some undef lanes" internally because that's (part of) the canonical way to represent certain SIMD operations in LLVM IR. If such a check is implemented and it fires on std::arch code, then we may have to add new intrinsics to express those patterns. (Which would be good, to be clear, I just want to note that this may be necessary to make the move.)</p>



<a name="201473600"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/213817-t-lang/topic/LLVM%20IR%20semantics/near/201473600" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> RalfJ <a href="https://rust-lang.github.io/zulip_archive/stream/213817-t-lang/topic/LLVM.20IR.20semantics.html#201473600">(Jun 20 2020 at 11:18)</a>:</h4>
<p>what I am interested in here (as usual) is the MIR semantics</p>



<a name="201473609"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/213817-t-lang/topic/LLVM%20IR%20semantics/near/201473609" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> RalfJ <a href="https://rust-lang.github.io/zulip_archive/stream/213817-t-lang/topic/LLVM.20IR.20semantics.html#201473609">(Jun 20 2020 at 11:19)</a>:</h4>
<p>if we have such things internally in <code>std::arch</code> that would mean MIR already supports OOB shuffles (and makes them undef or UB or something)</p>



<a name="201473612"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/213817-t-lang/topic/LLVM%20IR%20semantics/near/201473612" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> RalfJ <a href="https://rust-lang.github.io/zulip_archive/stream/213817-t-lang/topic/LLVM.20IR.20semantics.html#201473612">(Jun 20 2020 at 11:19)</a>:</h4>
<p>well looks like this needs an issue</p>



<a name="201473725"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/213817-t-lang/topic/LLVM%20IR%20semantics/near/201473725" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Hanna Kruppe <a href="https://rust-lang.github.io/zulip_archive/stream/213817-t-lang/topic/LLVM.20IR.20semantics.html#201473725">(Jun 20 2020 at 11:22)</a>:</h4>
<p>I don't think there's much use in trying to reverse engineer what the de facto MIR semantics of this intrinsics are today. There's (roughly) agreement what the semantics <em>ought</em> to be, and I'm just pointing out we may need some extra intrinsics to actually implement and enforce the desirable semantics.</p>



<a name="201473914"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/213817-t-lang/topic/LLVM%20IR%20semantics/near/201473914" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> RalfJ <a href="https://rust-lang.github.io/zulip_archive/stream/213817-t-lang/topic/LLVM.20IR.20semantics.html#201473914">(Jun 20 2020 at 11:28)</a>:</h4>
<p>so, like this? <a href="https://github.com/rust-lang/rust/issues/73542">https://github.com/rust-lang/rust/issues/73542</a></p>



<a name="201473929"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/213817-t-lang/topic/LLVM%20IR%20semantics/near/201473929" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Hanna Kruppe <a href="https://rust-lang.github.io/zulip_archive/stream/213817-t-lang/topic/LLVM.20IR.20semantics.html#201473929">(Jun 20 2020 at 11:29)</a>:</h4>
<p>LGTM</p>



<a name="201481245"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/213817-t-lang/topic/LLVM%20IR%20semantics/near/201481245" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Josh Triplett <a href="https://rust-lang.github.io/zulip_archive/stream/213817-t-lang/topic/LLVM.20IR.20semantics.html#201481245">(Jun 20 2020 at 15:04)</a>:</h4>
<p>Trying to make sure I understand something. Is this about SIMD operations that run off the end of a slice, and then assume that at a machine level they won't touch the bits that came from past the end?</p>



<a name="201481261"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/213817-t-lang/topic/LLVM%20IR%20semantics/near/201481261" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Josh Triplett <a href="https://rust-lang.github.io/zulip_archive/stream/213817-t-lang/topic/LLVM.20IR.20semantics.html#201481261">(Jun 20 2020 at 15:05)</a>:</h4>
<p>Or am I missing the nature of the OOB operations here?</p>



<a name="201482929"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/213817-t-lang/topic/LLVM%20IR%20semantics/near/201482929" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Hanna Kruppe <a href="https://rust-lang.github.io/zulip_archive/stream/213817-t-lang/topic/LLVM.20IR.20semantics.html#201482929">(Jun 20 2020 at 15:45)</a>:</h4>
<p>No memory accesses. Just vector -&gt; vector shuffles. There's more discussion in the issue Ralf created.</p>



<a name="201483448"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/213817-t-lang/topic/LLVM%20IR%20semantics/near/201483448" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Josh Triplett <a href="https://rust-lang.github.io/zulip_archive/stream/213817-t-lang/topic/LLVM.20IR.20semantics.html#201483448">(Jun 20 2020 at 15:56)</a>:</h4>
<p>I read through that whole issue, and the linked blog post, and didn't see what "OOB masks" meant.</p>



<a name="201483464"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/213817-t-lang/topic/LLVM%20IR%20semantics/near/201483464" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Josh Triplett <a href="https://rust-lang.github.io/zulip_archive/stream/213817-t-lang/topic/LLVM.20IR.20semantics.html#201483464">(Jun 20 2020 at 15:56)</a>:</h4>
<p>So, something like using a mask value of 12 with a vector register containing 8 values?</p>



<a name="201483588"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/213817-t-lang/topic/LLVM%20IR%20semantics/near/201483588" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> RalfJ <a href="https://rust-lang.github.io/zulip_archive/stream/213817-t-lang/topic/LLVM.20IR.20semantics.html#201483588">(Jun 20 2020 at 15:59)</a>:</h4>
<p><span class="user-mention" data-user-id="239881">@Josh Triplett</span> this is about an operation like this:</p>
<div class="codehilite"><pre><span></span><code>simd_shuffle4(x, y, [0,4,7,9])
</code></pre></div>


<p>The indices in the last argument refer to the first two arguments' elements, and as such can be OOB.</p>



<a name="201483608"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/213817-t-lang/topic/LLVM%20IR%20semantics/near/201483608" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Josh Triplett <a href="https://rust-lang.github.io/zulip_archive/stream/213817-t-lang/topic/LLVM.20IR.20semantics.html#201483608">(Jun 20 2020 at 15:59)</a>:</h4>
<p>Got it, thank you.</p>



<a name="201483683"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/213817-t-lang/topic/LLVM%20IR%20semantics/near/201483683" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Josh Triplett <a href="https://rust-lang.github.io/zulip_archive/stream/213817-t-lang/topic/LLVM.20IR.20semantics.html#201483683">(Jun 20 2020 at 16:00)</a>:</h4>
<p>I agree with you that that doesn't seem like something we need to support.</p>



<a name="201494570"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/213817-t-lang/topic/LLVM%20IR%20semantics/near/201494570" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Jake Goulding <a href="https://rust-lang.github.io/zulip_archive/stream/213817-t-lang/topic/LLVM.20IR.20semantics.html#201494570">(Jun 20 2020 at 19:59)</a>:</h4>
<blockquote>
<p>SIMD operations that run off the end of a slice, and then assume that at a machine level they won't touch the bits that came from past the end?</p>
</blockquote>
<p>Is there another issue discussing this? It’s relevant to my crates.</p>



<a name="201498165"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/213817-t-lang/topic/LLVM%20IR%20semantics/near/201498165" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Lokathor <a href="https://rust-lang.github.io/zulip_archive/stream/213817-t-lang/topic/LLVM.20IR.20semantics.html#201498165">(Jun 20 2020 at 21:17)</a>:</h4>
<p><span class="user-mention" data-user-id="116155">@Jake Goulding</span> I don't think you can do that in general, based on my limited understanding of the situation, but you should write out your scenario as a thread of its own probably.</p>



<a name="201526694"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/213817-t-lang/topic/LLVM%20IR%20semantics/near/201526694" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> RalfJ <a href="https://rust-lang.github.io/zulip_archive/stream/213817-t-lang/topic/LLVM.20IR.20semantics.html#201526694">(Jun 21 2020 at 09:39)</a>:</h4>
<p><span class="user-mention" data-user-id="116155">@Jake Goulding</span> I think <a href="https://github.com/rust-lang/unsafe-code-guidelines/issues/2">https://github.com/rust-lang/unsafe-code-guidelines/issues/2</a> is what you are looking for</p>



<a name="201526696"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/213817-t-lang/topic/LLVM%20IR%20semantics/near/201526696" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> RalfJ <a href="https://rust-lang.github.io/zulip_archive/stream/213817-t-lang/topic/LLVM.20IR.20semantics.html#201526696">(Jun 21 2020 at 09:39)</a>:</h4>
<p>the summary is, I have no idea how to do this given LLVM's semantics</p>



<a name="201526702"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/213817-t-lang/topic/LLVM%20IR%20semantics/near/201526702" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> RalfJ <a href="https://rust-lang.github.io/zulip_archive/stream/213817-t-lang/topic/LLVM.20IR.20semantics.html#201526702">(Jun 21 2020 at 09:39)</a>:</h4>
<p>so this would likely need someone to push a corresponding change through LLVM first</p>



<a name="201528666"></a>
<h4><a href="https://rust-lang.zulipchat.com#narrow/stream/213817-t-lang/topic/LLVM%20IR%20semantics/near/201528666" class="zl"><img src="https://rust-lang.github.io/zulip_archive/assets/img/zulip.svg" alt="view this post on Zulip" style="width:20px;height:20px;"></a> Jake Goulding <a href="https://rust-lang.github.io/zulip_archive/stream/213817-t-lang/topic/LLVM.20IR.20semantics.html#201528666">(Jun 21 2020 at 10:36)</a>:</h4>
<p>Yes that looks relevant. Thank you.</p>



<hr><p>Last updated: Aug 07 2021 at 22:04 UTC</p>
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